1. Field of the Invention
This invention relates generally to signal generation and more specifically to the synthesis of periodic signals with high signal integrity.
2. Description of the Related Art
Automatic test equipment (ATE) and other high performance electronic systems rely upon the ability to generate precise periodic signals. ATE requires these signals for testing state-of-the-art electronic devices, such as computer chips, telecommunications chips, and electronic assemblies. As these devices and assemblies become more advanced, ATE must commensurately advance to maintain high testing standards.
FIG. 1 shows a conventional architecture 100 used by many ATE systems for synthesizing precise periodic signals. The architecture 100 includes a frequency generator 110, such as a DDS (direct digital synthesizer). The frequency generator 110 receives a programming value FREF and generates an analog signal having a frequency FIN, which is proportional to FREF. The signal having frequency FIN is then fed to one or more phase-locked loops 112–118. Each phase-locked loop 112–118 produces a respective output signal having a frequency FOUT that is proportional to FIN. The architecture 100 thus provides a way of generating numerous signals of different frequencies, but which are all derived from a common frequency, FIN.
FIG. 2 shows a conventional phase-locked loop 200, such as may be used in the architecture 100 of FIG. 1. The phase-locked loop 200 receives an input signal having a frequency FIN and generates an output signal having a frequency FOUT. The phase-locked loop 200 is a feedback circuit having a forward path and a feedback path. The forward path includes a phase detector 210, a high gain loop filter 212, and a voltage-controlled oscillator (VCO) 214. The feedback path generally includes a first frequency divider 218. This divider in the feedback path has the effect of multiplying the output frequency. A second frequency divider 216 may optionally be provided outside the feedback loop for dividing the output frequency.
The phase detector 210 receives two input signals: the input signal at frequency FIN and a feedback signal at frequency FOUT/M. As is known, the phase detector 210 includes circuitry for comparing the phase of its input signals to produce an output signal proportional to the difference in phase between its input signals. If properly stabilized, the action of the feedback loop drives this phase difference to zero. The loop filter 212 smoothes the output of the phase detector 210 and generally rolls off the gain of the loop to establish stability. The VCO 214 converts the output of the loop filter into a sinusoid to produce FOUT. The first divider 218 (generally a counter) divides FOUT by M to produce the feedback signal. The second divider 216, if one is provided, divides FOUT by N. The overall closed loop frequency gain of the phase-locked loop 200 is therefore M/N.
We have recognized that the conventional architecture 100 for generating periodic signals can suffer from certain deficiencies. For instance, the phase-locked loop 200 introduces noise, which appears as timing jitter on synthesized output signals. The noise originates from several sources. For instance, the high-gain loop filter 212 introduces noise. It also amplifies noise generated internally and from other sources. The phase detector 210, VCO 214, first divider 218, and second divider 216 of the phase-locked loop 200 also add substantial noise.
Another problematic aspect of the conventional architecture 100 is that the divider 218 of the phase-locked loop 200 directly reduces the phase-locked loop's open loop gain. It is generally desirable for the divider ratio M to be large, to provide fine control over output frequency. However, the larger the value of M, the greater the reduction in open loop gain. As open loop gain is decreased, the accuracy and speed of the phase-locked loop 200 are correspondingly reduced.
It would be desirable to overcome these deficiencies.